making an IP for DMA transfers

Yep should be easy to do. I'm guessing the 16b to 32b FIFO uses flow control similar to Avalon ST. So it should be a matter of making the 32b side ST compliant and removing the secondary FIFO. If possible I would try to make the traceiver to FIFO interface ST compliant, if that's possible then I think there is a FIFO component in Qsys that supports different data widths on each side which you could use instead and not have to worry about custom FIFO logic.