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Altera_Forum's avatar
Altera_Forum
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15 years ago

m_state==STATE_DEBUG, cause by sram instability ?

Hi,

I have some problems to program (run as/debug as) my Nios design with Eclipse IDE: quite often I have this message :

"m_state==STATE_DEBUG..."

Sometimes I can program successfully and continuously 10,20,30... times and suddenly I can't for 1, 2 or 20 times...

I use :

- Terasic blaster or altera usb blaster rev C, both work with other custom boards or eval boards

- quartus / nios ide 9.1 sp1

- nios host on external sram

- custom board with jtag circuit copied from nios 2 cyclone II eval board :

-> 1k pull up on TDI, TMS

-> 1k pull down // 10pF on tck

I have added 10pF capacitors on other signals (TDI, TMS, TDO) without results.

I see other threads (old) and this page :

http://www.altera.com/support/kdb/solutions/rd05242010_978.html?gsa_pos=1&wt.oss_r=1&wt.oss=m_state

But it doesn't help me, I don't see what could be wrong in my jtag circuitry or blaster.

I also have some problems of stability with my external sram (no ideas of the reasons):

http://www.alteraforum.com/forum/showthread.php?t=28195

I wonder if a problem with the sram could generate this "random" error ?

Thanks a lot for helping, I am really stuck with my nios problems.

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The AN JAB mentioned should certainly be followed, but you should also take care that other major system buses/interfaces are not interfering (crosstalk) with JTAG communication.

    - I've seen that sort of mistake several times.

    Cheers,

    slacker
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks for your answers.

    The Application note is really interesting and well illustrated.

    Jtag traces and some sram addresses traces are on the same area on different layers on the PCB. Maybe This could explain my problems : jtag error when downloading or bad sram accesses during running.

    I will make some measures and search in this way. Thanks for Advices.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    If you use any custom components make sure to simulate them to ensure they properly heed waitrequest. If they violate the spec the simulation should end with an assertion message.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    My board is custom but components are "common" : cyclone III ep3c25, sram cypress cy7c1380d, flash epcs16. The design is inspired by datasheets and an altera evaluation board (for the sram).