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Altera_Forum
Honored Contributor
16 years agom_state == STATE_DEBUG Error
I build a SOPC system which consists of a Nios II cpu, onchip memory and jtag uart component with frequency of 100MHz driving all the components. The system works fine when I run the count binary pro...
Altera_Forum
Honored Contributor
15 years agoI would signaltap the Nios II data master interface and figure out if it's becoming stuck (read/write issued with waitrequest stuck high). If it is stuck look at the address being issued during the access and then work your way from there. It's a bit of a pain debugging this way since it requires recompilation of the design so if you can solve it down to the point that it's just any access to a particular component causing these I would move over simulation so that you can look at everything all at once.