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Altera_Forum
Honored Contributor
19 years agoI ran into a similar problem, although in my case it appeared that the ISR/DSR could keep up with the 115200 baud rate, but the application rarely ran and so the internal read buffer overflowed. Increasing that size may work if your data is bursty.
I switched to the OpenCore.org 16550 UART with wishbone interface. This uses the standard ecos 16550 drivers. It is fairly easy to make this an Avalon SOPC component. Download the core, read the errata and make the appropriate code changes, and then create a new Component. Load the verilog files and specify the uart_top as the top module. You will then need to assign the wishbone signals to the avalon slave interface. Most are fairly obvious, but wb_stb_i and wb_cyc_i are avalon chipselect and wb_ack_0 is waitrequest_n. If you are connecting to a 32 bit avalon bus there may be gaps between the registers that you need to account for in the driver and the baud rate divisor is dependent on the Avalon Bus speed. If you have an Altera FAE they can send you an Avalon SOPC module of an older version of the UART core as a starting point.