Long Boot Time after update to 5.0

after updating to Quartus / NIOS II 5.0 my design needs about 7 seconds to boot (reboot) from EPCS. With an oscilloscope I've measured, that the FPGA configuration is done in 80 msec. After a short pause of 150 msec the bootloader starts to load the firmware from EPCS into SRAM. This procedure lasts now 7 seconds.

The serial clock on EPCS shows that every 120 usec one byte is serial shifted out (120usec x 65250 = 7 sec total)

The previous version had a repetitive rate of 1,25 usec (= 81msec total )

Facts:

- Reset signal is stable (PLL with locked-detection)

- both, design and custom board are re-compiled with new version 5.0

- EPCS programming is done via Flash-Programmer

- Environment variables are set to Quartus50

- firmware size: 65250 bytes

- Reset Address set to EPCS

- Exception Address set to SRAM

- Firmware starts immediately after download ends

- previous version (4.2 / NIOS II 1.1) needs 200msec total to start.

- system clock is 49.15 MHz

- all linker sections set to SRAM

Any suggestions ?

Mike

added due to new experiences :

- reading from EPCS via HAL ( alt_read_flash() ) is also extremly slow!