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Altera_Forum's avatar
Altera_Forum
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20 years ago

Long Boot Time after update to 5.0

after updating to Quartus / NIOS II 5.0 my design needs about 7 seconds to boot (reboot) from EPCS. With an oscilloscope I've measured, that the FPGA configuration is done in 80 msec. After a sho...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

MiR,

Oops, you are correct about the class.ptf. Thanks for that; I'll edit the text I have above to work around this.... we 'make' the .pm file to generate the .ptf with its default parameters and that is where my instructions were flawed.

Also thanks for the tip about the flash programmer! That is really useful although the speed never bothered me... probably because it was on-par with CFI flash programming latency.

To address your question - it was a bug masking a bug. In 5.0 several fixes were put into the SPI controller that basically excited this bug. Previously with 'extradelay' set, the 'extra delay' was not occuring in all cases as it should have, depending on the state of various SPI controller register bits (it was a pretty rarely used feature from what I'm told). With 'extra delay' now in affect for all SPI transfers, the bogus parameter in the epcs/asmi logic started delaying things.