Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

Logic elements -> RAM blocks

I have a design where I use some arrays of integers(VHDL) to store data. When I synthesize the design, the arrays are implemented as logic cells, but I would rather have them as RAM blocks. Is there ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

OK, after thinking about it once more, I noticed that I sometimes access two different array fields in one cycle. Translating this behaviour to RAM is probably a little too tough for the compiler. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/smile.gif