Honored Contributor
Honored ContributorOK, just to understand this:
A write-request doesn't wait for an "ack" and the next write-request can start immediately. The "ack" can be transfered while the next write is already in progress. A read-request has to wait for the result of the read-request before a new transaction can start, correct? And this is why a read-request takes about 15 times more time. It just has to wait until every transaction is finished. Did I get this right? And this gives me the next question: (I'm sorry, I'm more into hardware, this is also why i prefer to draw BDF-Files) How do I alias the fifo? Is this done in Software or in the design? Because I don't see any option for the fifo which means "alias". My main Problem is that I have to fill and empty the fifo very quick (about 1GBit/s). But not the whole time. I have much latency in my communication, only about 50% of the time is used for communication. Do you have experience in the PCIe hip? There are so many connections I don't use. Is my wiring correct for simple purposes?
