Linux-Driver for Altera PCIe HIP or simple methode to access PCIe

Now I have a little speed problem:

I made a design in qsys where a 32bit fifo is connected to the avalon bus on both sides (in and out). It has a depth of 8192.

With a litte addidion I used the pci_debug - program to messure the time for write and read operations with the following code:

		
                errorcounter=0;
		writedata = 0x00000010;
		clock_gettime(CLOCK_REALTIME, &start);
		for (i=0; i<8190; i++)
		{
			*(volatile unsigned int *)(dev->addr + 0x09400000) = (writedata * i);
		}	
		clock_gettime(CLOCK_REALTIME, &end);
		clock1 = (unsigned long)(end.tv_nsec - start.tv_nsec);
		clock1sec = (unsigned long)(end.tv_sec - start.tv_sec);
		readdata = 0x00000010;
		clock_gettime(CLOCK_REALTIME, &start);
		for (i=0; i<8190; i++)
		{
			readdata =*(volatile unsigned int *)(dev->addr + 0x09400040); 
		}
		clock_gettime(CLOCK_REALTIME, &end);
		clock2 = (unsigned long)(end.tv_nsec - start.tv_nsec);
		clock2sec = (unsigned long)(end.tv_sec - start.tv_sec);
		printf("Summary 32Bit Fifo:\n");
		printf("8190 Cells written in %.2ld s and %.9ld ns.\n", clock1sec, clock1);
		printf("8190 Cells read in    %.2ld s and %.9ld ns.\n", clock2sec, clock2);

To my surprise the 8190 writes took 792 us (that makes about 41MB/s) and the reades took 11869 us (that makes about 2.8 MB/s).

Why is it so slow?

To my design:

I used the "QSYS PCIe to ext memory" reference design and reduced it to PCIe 1x and the clock sources. Then I added the fifo.

The Design works but it seems that it is slow as hell. Is there something I've done wrong or how else can I speed up the design?

https://www.alteraforum.com/forum/attachment.php?attachmentid=6816

I want to use a schematic file for my top-level design-file so I tried to translate the original file to a BDF-File:

https://www.alteraforum.com/forum/attachment.php?attachmentid=6817

Have I forgotten something?