Honored Contributor
Honored ContributorI don't remember exactly what I did. I think the include file was missing some parts and the perl generator was bugged. I don't know how to add files to a post so I will just paste the code:
With this I just compiled the kernel and started uclinux but I haven't used it yet. I am supposed to play with this next week. So if you manage to make it work I would be interested to know ;-) Also if there is an official fix I'm interested too. Marc File: altera\kits\nios2\bin\eclipse\plugins\com.microtronix.nios2linux.kernel_0.1.5\linux-2.6.x\include\asm-nios2nommu\spi.h#ifndef _ASM_SPI_H_# define _ASM_SPI_H_ 1
/*--------------------------------------------------------------------
*
* include/asm-nios2nommu/spi.h
*
* Derived from various works, Alpha, ix86, M68K, Sparc, ...et al
*
* Copyright (C) 2004 Microtronix Datacom Ltd
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*
* Jan/20/2004 dgt NiosII
*
---------------------------------------------------------------------*/
# include <asm/nios.h>
int register_NIOS_SPI( void );
void unregister_NIOS_SPI( void );
# if defined(MODULE)
void cleanup_module( void );
int init_module( void );# endif
# if defined(__KERNEL__)
int spi_reset ( void );# endif
# define clockCS 0x01# define temperatureCS 0x02
# define clock_read_base 0x00# define clock_write_base 0x80# define clock_read_control 0x0F# define clock_read_trickle 0x11
# define clock_read_sec 0x00# define clock_read_min 0x01# define clock_read_hour 0x02# define clock_read_day 0x03# define clock_read_date 0x04# define clock_read_month 0x05# define clock_read_year 0x06
# define clock_write_control 0x8F# define clock_write_trickle 0x91# define clock_write_sec 0x80# define clock_write_min 0x81# define clock_write_hour 0x82# define clock_write_day 0x83# define clock_write_date 0x84# define clock_write_month 0x85# define clock_write_year 0x86
# define clock_write_ram_start 0xA0# define clock_write_ram_end 0x100# define clock_read_ram_start 0x20# define clock_read_ram_end 0x80
# define clock_sec_def 0x11# define clock_min_def 0x59# define clock_hour_def 0x71# define clock_day_def 0x00# define clock_date_def 0x20# define clock_month_def 0x12# define clock_year_def 0x34
# define temp_read_base 0x00# define temp_write_base 0x80# define temp_read_control 0x00# define temp_write_control 0x80# define temp_read_msb 0x02# define temp_read_lsb 0x01
# define MAX_TEMP_VAR 10
// SPI Registers
typedef volatile struct
{
int np_spirxdata; // Read-only, 1-16 bit
int np_spitxdata; // Write-only, same width as rxdata
int np_spistatus; // Read-only, 9-bit
int np_spicontrol; // Read/Write, 9-bit
int np_spireserved; // reserved
int np_spislaveselect; // Read/Write, 1-16 bit, master only
int np_spiendofpacket; // Read/write, same width as txdata, rxdata.
} np_spi;
// SPI Status Register Bits
enum
{
np_spistatus_eop_bit = 9,
np_spistatus_e_bit = 8,
np_spistatus_rrdy_bit = 7,
np_spistatus_trdy_bit = 6,
np_spistatus_tmt_bit = 5,
np_spistatus_toe_bit = 4,
np_spistatus_roe_bit = 3,
np_spistatus_eop_mask = (1 << 9),
np_spistatus_e_mask = (1 << 8),
np_spistatus_rrdy_mask = (1 << 7),
np_spistatus_trdy_mask = (1 << 6),
np_spistatus_tmt_mask = (1 << 5),
np_spistatus_toe_mask = (1 << 4),
np_spistatus_roe_mask = (1 << 3),
};
// SPI Control Register Bits
enum
{
np_spicontrol_sso_bit = 10,
np_spicontrol_ieop_bit = 9,
np_spicontrol_ie_bit = 8,
np_spicontrol_irrdy_bit = 7,
np_spicontrol_itrdy_bit = 6,
np_spicontrol_itoe_bit = 4,
np_spicontrol_iroe_bit = 3,
np_spicontrol_sso_mask = (1 << 10),
np_spicontrol_ieop_mask = (1 << 9),
np_spicontrol_ie_mask = (1 << 8),
np_spicontrol_irrdy_mask = (1 << 7),
np_spicontrol_itrdy_mask = (1 << 6),
np_spicontrol_itoe_mask = (1 << 4),
np_spicontrol_iroe_mask = (1 << 3),
};
// SPI Routines.
int nr_spi_rxchar(np_spi *spiBase);
int nr_spi_txchar(int i, np_spi *spiBase);
# endif /*_ASM_SPI_H_*/package altera_avalon_spi;
# This module renames the first altera_avalon_spi peripheral to spi
require PTF::SystemPTF;
require PTF::SystemPTF::Module;
use strict;
sub run {
my ($system, @spi_names) = @_;
my %module_map = (
"spi" => undef,
);
my @module_map_order = ("spi");
foreach my $module_name (@module_map_order) {
my $module = $system->getModule ($module_name);
# determine availability of each module_name
if ($module) {
my $class_name = $module->getClass ();
if ($class_name ne 'altera_avalon_spi') {
print "#error The module name $module_name is of class $class_name.\n";
print "#error This will break the kernel.\n";
print "#error Please rename the module to something else in SOPC Builder.\n\n";
} else {
print "/* No translation for $module_name necessary */\n\n";
}
} else {
# if module name is available, take first uart and translate
while (scalar (@spi_names) > 0) {
my $spi_name = shift (@spi_names);
if (!exists $module_map{$spi_name}) {
my $module = $system->getModule ($spi_name);
my $result;
print "/* Redefining $spi_name -> $module_name */\n";
# start outputing necessary strings
print "#undef na_" . $spi_name . "\n";
print "#undef na_" . $spi_name . "_irq\n";
print "\n";
# base address information
$result = $module->getBaseAddress ();
printf ("#define na_%-50s %#010x\n",
($module_name, hex ($result) | 0x80000000));
# irq information
$result = $module->getIRQ ();
printf ("#define na_%-30s %30s\n",
($module_name . "_irq", $result));
print "\n";
last;
}
}
}
}
}
1;
