jtag via usb

I'm not really sure what you are trying to do. Your entry makes no sense to me. The JTAG interface stuff is spit out by SOPC builder, check out jtag_debug_module.vhd file located in your project directory.

BTW, your jtag stuff lives on the FPGA, not the PLD. The PLD is used to program the FPGA from the flash because the eval board does not have a configuration device. The VHDL, or Verilog code using a PLD to configure the FPGA is available on their web site.

Doug