Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

jtag via usb

The Nios II Evaluation Kit is able to download its Jtag commands directly through its USB cable. Apparently it has implemented the USB Blaster functionality on a MAX EPM7064B CPLD which is on the evaluation board. This seems the way to go with respect to field upgrades - no additional hardware required other than the USB cable. I could implement this setup if I had one of two pieces of documentation:

The USB protocal or the VHDL for the MAX CPLD. Anybody with suggestion on how to procur these documents. No sign of them on the Altera website.

7 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    I'm not really sure what you are trying to do. Your entry makes no sense to me. The JTAG interface stuff is spit out by SOPC builder, check out jtag_debug_module.vhd file located in your project directory.

    BTW, your jtag stuff lives on the FPGA, not the PLD. The PLD is used to program the FPGA from the flash because the eval board does not have a configuration device. The VHDL, or Verilog code using a PLD to configure the FPGA is available on their web site.

    Doug
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Doug,

    What I'm looking for is the other half of the CPLD's function which is the serialization

    of the usb data coming from/to the PC. Otherwise known on the schematic block diagram as USB_BLASTER_CCT.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    I do not belive that Altera will ever provide the source for the cpld on the evaluation kit. Just because they want to sell their usb blaster and there are not a lot of free usb controller designs out there.

    For in field programming I would suggest a boot loader. Their are quite a few available for free that should fit your needs.

    --wolf
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Altera might be willing to give you access to this code, for a fee, but I seriously doubt that they would just give it away. After all, some money is made on the USB Blaster, right? :-)

    You might also take a look at what easyfpga (http://easyfpga.com/ezniosusb_features.htm) provides, though making it behave like a USB Blaster (on both the host and embedded side) will be tricky without Altera's help.

    Good luck!

    - slacker
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    If you are trying to get easy field upgradeability, you can write to the config. flash device through the Nios processor itself I believe - so that is the ultimate solution since it's soft; you can update through ethernet, serial etc. etc... you just need code to do some simple routines with the config flash.

    And I agree with others - I can't see altera giving away that sort of IP since it would undercut their USB Blaster sales (which must be quite good considering the relative simplicity of the USB blaster).
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    I have used the FTDI FT2232C (used by Easy FPGA) by myself to connect a FPGA to a usb port. It is a great device and even more important, very well documented.

    FTDI provides a dll that implements the JTAG protocol. It should not be that difficult to write a tool that sends data to the FPGA.

    --wolf
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    19 years ago

    I need to get the HDL code or *.sof design for the cpld in the altera usb blaster,Can you give me it.