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Altera_Forum
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19 years ago

JTAG UART dyslexia

Hi All, I made a very small design and I got some problem with the JTAG UART terminal output. I compiled a simple "Hello world" and everything works fine excepted that JTAG UART is "dyslexic" : i...
Altera_Forum's avatar
Altera_Forum
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19 years ago

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originally posted by slacker@Feb 1 2007, 06:57 AM

yes.... the sopc builder system clock has to be greater than twice the maximum jtag clock. depending on what download cable you're using, you might see up to 10mhz on the jtag clock.

- slacker

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Is there a way to slown down the JTAG clock (let&#39;s say downto 5MHz) via software option or does it only rely on my PC hardware?

Thx.