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Altera_Forum's avatar
Altera_Forum
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20 years ago

JTAG stopped working

When I try to download a program, I now get the error message

"There are no Nios II CPUs with debug modules available which match the values

specified. Please check that your PLD is correctly configured, downloading a

new SOF file if necessary."

Programming the config' device doesn't change matters. Active Serial is OK, but JTAG throws up the error "CONF_DONE pin failed to go high in device 1". How can this be when using JTAG?

I'm using AS/JTAG programming, as indicated in cfg_cf52009.pdf, page 9-7

Quartus-II V5.0 Build 148

NIOS-II IDE V5.0 Build 73C

What has changed is that the software has grown significantly, and, out of 20 attempts, I managed to get it to JTAG-debug once, with the board virtually plugged into the parallel port.

What kind of rise times should I be seeing on the JTAG signals?

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    Sorted.

    Put a 10k pullup to 3v3 on the TDO signal, and slugged TCK with 33pF.

    Given the problems I've had, does anyone think it's worth using a Schmitt buffer on the board to ensure no glitches appear on the TCK line?
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    20 years ago

    Since you mention the parallel port, I gather you're not using a USB Blaster... :-)

    Cheers,

    - slacker
  • Altera_Forum's avatar
    Altera_Forum
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    20 years ago

    I've run into similar problems, its been the layout of the JTAG connector to the FPGA. You can generally fix it by isolating the clock line (cut both ends of the trace) and add a jumper wire.

    George