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Altera_Forum's avatar
Altera_Forum
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20 years ago

Jtag debug problem... any suggestion welcome.....

I'm working on my board designed with NiosII and Ep1C20 device, extarnal 16 bit flash and 32 bit dram. I check the tco e tsu for pll shift dram clock, from timing analyzer will be work at 100M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

i spent also a lto of time for this problem, the strange thing is that was working with fpga loading and flash programmer, but not on uart jtag usage. The series resistor my be fine also, in any case this interface is too much criitical......... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/dry.gif

roby