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Altera_Forum's avatar
Altera_Forum
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21 years ago

Jtag debug problem... any suggestion welcome.....

I'm working on my board designed with NiosII and Ep1C20 device, extarnal 16 bit flash and 32 bit dram. I check the tco e tsu for pll shift dram clock, from timing analyzer will be work at 100M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

There are also some proposals from Altera application engineer

that sometimes a small series resistor (about 32ohms) in DCLK helps

, so placing a R-C combination in layout is a good idea.