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Altera_Forum's avatar
Altera_Forum
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20 years ago

Jtag debug problem... any suggestion welcome.....

I'm working on my board designed with NiosII and Ep1C20 device, extarnal 16 bit flash and 32 bit dram. I check the tco e tsu for pll shift dram clock, from timing analyzer will be work at 100M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

The problem was solved, a small capacitor (100 pF) from Jtag clock and ground solve the bug. I think this is do to some glich or noise, i don't like this type of solution , is not "clean" but is the only one that i found. I'm using the USB blaster Rev.B my be a problem of ICE jtag, on my board i have only the port connected to fpga with short trace.

Note that only in uart jtag mode we see the problem, not during fpga loading and not during flash programming with the tools inside the IDE. ( it use jtag uart also ???), my be legated to different signal speed in jtag, in any case this interface is very critical.

Roby