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Altera_Forum
Honored Contributor
Honored ContributorJtag debug problem... any suggestion welcome.....
I'm working on my board designed with NiosII and Ep1C20 device, extarnal 16 bit flash and 32 bit dram. I check the tco e tsu for pll shift dram clock, from timing analyzer will be work at 100M...
Altera_ForumHonored Contributor
Honored ContributorI try to realize a smal project with sram block inside ad minimum requirements, i choose internal ram as target in IDE library properties but the result is the same..... http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/mad.gif
roby
