Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Jtag debug problem... any suggestion welcome.....

I'm working on my board designed with NiosII and Ep1C20 device, extarnal 16 bit flash and 32 bit dram. I check the tco e tsu for pll shift dram clock, from timing analyzer will be work at 100M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Yesss, i have programmed the flash with flash programmer inside the IDE and HW custom project as target.

If there are not other way to understan the origin of problem i will follow your suggestion , a restricted design with only the nios core, flash interface and onchip memory............ http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/unsure.gif