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Altera_Forum's avatar
Altera_Forum
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20 years ago

Jtag debug problem... any suggestion welcome.....

I'm working on my board designed with NiosII and Ep1C20 device, extarnal 16 bit flash and 32 bit dram. I check the tco e tsu for pll shift dram clock, from timing analyzer will be work at 100M...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
20 years ago

I have to ask.... you added an OCI core to your system right (in the Nios II settings)

Also you are programming the correct hardware right? (if you are downloading/debuging software immediately after Flash programming, you may have the flash programmer hardware still in the FPGA <-- I&#39;m assuming you are using the IDE for flash programming)

Usually bringing up new systems I start small (CPU, onchip memory, JTAG Uart, SystemID, etc...) then add in more components so that I&#39;m not debugging 10+ components at once.