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Altera_Forum
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16 years ago

JTAG conflict when debugging dual NiosII system

We have a dual NiosII arhitecture implemented on a Altera StratixIII dev. kit. The processors only share a dual port ram for communciation, i.e. each (cpuA and cpuB) has its own ram and rom, everythi...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Make sure to load the .jdi file for each application project before debugging the code. This will make sure the debugger knows which processor debug module is being targeted. It could be that the IDE is trying to attach to the debugger of the wrong CPU. The load .jdi file is in the 2nd 'debug as' menu.

Each debugger will have a unique instance ID which is how the tools distinguish the various JTAG IP that you have in the FPGA. Search for "JTAG" in this document and you'll find out a little bit more about this.

http://www.altera.com/literature/hb/nios2/edh_ed_handbook.pdf