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Altera_Forum
Honored Contributor
Honored Contributorissue with program executing from SDRAM with NiosII/f core(cache4KB)
Hi, I am using a NiosII fast core with cache size 4KB. i have an SDRAM controller. The system frequency is 50MHz. SDRAm freq=50MHz. The Issue is when the program, data, R/W memory is made as S...
Altera_ForumHonored Contributor
Honored Contributorgood that you found a solution.
but -45 is nealy the same value but the opposit direction than your 39 degree pahse shift. are you shure your calculation gave you +39 degree ? one thing you can check and should check to be shure the phase shift is with a correct range, cool down the design. this will show if the hold timing works, as cooler chips are getting faster ...
