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Altera_Forum
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16 years ago

issue with program executing from SDRAM with NiosII/f core(cache4KB)

Hi, I am using a NiosII fast core with cache size 4KB. i have an SDRAM controller. The system frequency is 50MHz. SDRAm freq=50MHz. The Issue is when the program, data, R/W memory is made as S...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Hi All,

Thank you for your suggestions. i was able to resolve the issue with the SDRAM by changing the SDRAM clk phase lag w.r.t to the controller clock by trial and error method. the clock now given is -45 degree w.r.t controller clock.

Thanks Again...

Regards,

Shubha