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Altera_Forum
Honored Contributor
16 years agoissue with program executing from SDRAM with NiosII/f core(cache4KB)
Hi, I am using a NiosII fast core with cache size 4KB. i have an SDRAM controller. The system frequency is 50MHz. SDRAm freq=50MHz. The Issue is when the program, data, R/W memory is made as S...
Altera_Forum
Honored Contributor
16 years agoHi all,
thanks for the suggestions. i have changed the timing parameters of the SDRAM as per the datasheet and as specified in the controller. the clock phase is given as 2.18 ns (around 39.24 degree). but still i have the samw issue. i have only SDRAM as memory and no other memory for text and data. Shubha