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Altera_Forum
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16 years ago

issue with program executing from SDRAM with NiosII/f core(cache4KB)

Hi, I am using a NiosII fast core with cache size 4KB. i have an SDRAM controller. The system frequency is 50MHz. SDRAm freq=50MHz. The Issue is when the program, data, R/W memory is made as S...
Altera_Forum's avatar
Altera_Forum
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16 years ago

To properly test memory I would also slam it with DMA accesses with known memory test patterns like PRBS, 0x5A, etc... First get a CPU test running and then move on to the DMA test.