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Honored Contributor
Honored Contributorissue with program executing from SDRAM with NiosII/f core(cache4KB)
Hi, I am using a NiosII fast core with cache size 4KB. i have an SDRAM controller. The system frequency is 50MHz. SDRAm freq=50MHz. The Issue is when the program, data, R/W memory is made as S...
Altera_ForumHonored Contributor
Honored Contributorit is probably an sdram timing issue. when downloading and verifying the read / write speeds are very slow and never back to back. Without a cache, nios will also never have read or write transactions occur consecutively.
With the cache enabled, burst transactions occur, which can cause sdram timing issues to be exhibited. it is best to test the sdram interface with a dm type transaction. --dalon
