ISR execution

Hi eliben

Interrupts are automatically disabled means that the IE bit in the status register is cleared before executing the first instruction placed on the exception address. At the time the "eret" instruction is issued, the interrupts come back on, because the estatus register is copied to the status register.

If interrupts are enabled again or not, depends on the code executed from the exception address.

I think the default provided Altera interrupt handler is not reenabling interrupts. But you can write your own if you want.

Stefaan