Forum Discussion
5 Replies
- Altera_Forum
Honored Contributor
If you add too many Avalon slaves then your reduce fMax.
But more likely you've done something stupid :-) - Altera_Forum
Honored Contributor
There isn't a maximum, but if you add to many peripherals without pipelines it may become difficult to meet the timing requirements.
Is your design properly constrained and does Timequest say it meets the timing requirements? - Altera_Forum
Honored Contributor
or Avalon MM bridges
- Altera_Forum
Honored Contributor
Thank for replies,
Actually I think its a Fmax problem or my design is not constrained correctly. I'am verifying my design : timequest and avalon MM bridges. Thank you. Vincent. - Altera_Forum
Honored Contributor
After checking my design (constrained timequest etc...) and read "user guide SOPC Builder" and "instantiating The Nios II Processor in SOPCBuilder" , I solved my problem.
I think the AVALON pipeline bridges are not necessary for my design. We need every IO port is connected to the CPU instruction_master in SOPC_builder even if it takes a little more than the resources. My design work and the Fmax is the same. thank you for your ideas. :o Vincent.