Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributoris signed type definition synthesizable?
Hi all, I'm designing a simple divider as shown below: module divider (in1, in2, division, multiply); //parameter parameter DATA_WIDTH = 32; //Input input signed [DATA_WIDTH-...
Altera_ForumHonored Contributor
Honored ContributorIt's a Quartus feature to infer a divider MegaFunction from Verilog and VHDL (the latter with ieee.numeric_std) code. But it's limited in part, there's no easy way to control pipelining for the inferred divider (although possible, as shown in a previous forum thread).
