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Altera_Forum
Honored Contributor
Honored Contributoris signed type definition synthesizable?
Hi all, I'm designing a simple divider as shown below: module divider (in1, in2, division, multiply); //parameter parameter DATA_WIDTH = 32; //Input input signed [DATA_WIDTH-...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- Yes it is synthesizable. But it builds combinatorial logic (slow). This is due to the assign, and not due to the signed types. You should register it and pipeline it, to make it faster. --- Quote End --- Are you sure that the division is synthesizable? Is this a general Verilog feature or it is a charcteristic of the synthesis tool?
