Hi all, I have build an application on Stratix II, with three CPU&#39;s. I have ONE (!) pio line connected to the system of three CPU&#39;s. In the SOPC builder I connected the three CPU&#39;s to the PIO module. I enabled the IRQ on edge capture. All three CPU&#39;s are handling the interrupt. Now i&#39;m experiencing problems. My system hangs sometimes in the alt_irq_register.c file in the while loop below. I think it is because all CPU&#39;s are handling the interrupt and using this method to reset the register: IOWR_ALTERA_AVALON_PIO_EDGE_CAP(SYNC_CLOCK_BASE, 0x00); Can this be the problem? Does anyone have experienced the same problems before? I need to have the interrupts on all CPU&#39;s. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif The code in alt_irq_register.c (158) do { if (active & mask) { alt_irq(alt_irq_arg, i); break; } mask <<= 1; i++; } while (1);

Your problem is that the interrupt will interrupt all three CPUs, but obviously they don&#39;t all reach the ISR at the same time. One CPU will be first and will have cleared the interrupt before the other ISRs get in, so the software in the ISR will read that there is no active interrupt The interrupt handler is coded to assume that there must have been an active interrupt, however on some of your CPUs this will not be the case. You could recode the ISR, but you really need to give some more thought to what you&#39;re trying to do and design some hardware to cope with one interrupt source going to multiple CPUs

Hi jmastron, I think u could use three different PIO connected to each CPU, and then connect together your PIO signals, maybe outside SOPC builder... it&#39;s only an idea...

I&#39;m afraid I don&#39;t see how having more PIO helps. You need to think about how you wish the interrupt to be cleared, do you want the IRQ to interrupt all 3 processors and remain asserted until they have all seen it, or do you just want it to be cleared when one of them has processed it. The hardware and software will be completely different depending on what you&#39;re trying to do.

I want the interrupt to be received by all CPU&#39;s before clearing it. Is there a way to implement this?

Why don&#39;t you design some hardware which takes in the IRQ routes it to 3 signals which connect to each CPU. Have 3 slaves one for each CPU and the IRQ remains active on each CPU until you write to the slave to clear it.

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Altera_Forum

Honored Contributor

20 years ago

IRQ handler problem

Hi all,

I have build an application on Stratix II, with three CPU's. I have ONE (!) pio line connected to the system of three CPU's.

In the SOPC builder I connected the three CPU's to the PIO module. I enabled the IRQ on edge capture.

All three CPU's are handling the interrupt. Now i'm experiencing problems. My system hangs sometimes in the alt_irq_register.c file in the while loop below.

I think it is because all CPU's are handling the interrupt and using this method to reset the register:

      
IOWR_ALTERA_AVALON_PIO_EDGE_CAP(SYNC_CLOCK_BASE, 0x00);

Can this be the problem? Does anyone have experienced the same problems before?

I need to have the interrupts on all CPU's. http://forum.niosforum.com/work2/style_emoticons/<#EMO_DIR#>/sad.gif

The code in alt_irq_register.c (158)

    
    do
    {
      if (active & mask)
      { 
        alt_irq(alt_irq_arg, i); 
        break;
      }
      mask <<= 1;
      i++;
    } while (1);

12 Replies

Altera_Forum
Honored Contributor
20 years ago
Using 3 PIOs will enable you to turn off each signal in turn. However you need the logic to disable/clear the original interrupting hardware, plus once all 3 CPUs have handled the IRQ you need to re-enable all 3 of your PIOs. This could be done in software, but you'd be much better off desiging a bit of logic to solve the problem.
Altera_Forum
Honored Contributor
20 years ago
Ok, I think i've misunderstood the original problem: i didn't think that i had to:
<div class='quotetop'>QUOTE </div>
--- Quote Start ---
disable/clear the original interrupting hardware[/b]
--- Quote End ---

but only to "edge-capture" an input signal, without having to clear some extern register.
bye

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IRQ handler problem

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