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Altera_Forum's avatar
Altera_Forum
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21 years ago

IRQ handler problem

Hi all, I have build an application on Stratix II, with three CPU's. I have ONE (!) pio line connected to the system of three CPU's. In the SOPC builder I connected the three CPU&#39...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

The problem is that if you have 3 CPUs and one interrupt source. The first CPU interrupted will clear the cause of the interrupt so that the 2nd and 3rd CPUs will enter their ISR and the cause of the interrupt will have gone away. So you need to design hardware that will only clear the interrupt line when all 3 CPUs have taken the ISR.