Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

IORD IOWR macros vs. memory access to peripherals

What is the point of the IORD and IOWR macros? I can access my custom Avalon peripherals using them, but it seems like I can't access them like the following: volatile alt_u32 *DEV_PTR = DEV_...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

If you have a waitrequest signal, I don't think that the read latency parameter is used by the switch fabric anyway.

If the waitrequest signal is low there is really no reason why the CPU should freeze. Are you sure that the address that you use in the IORD macro is actually the right one?

Are the CPU data master and your custom component on the same clock domain? If not, could you check if the clock for your component's slave interface is actually running?

Is your design properly constrained and does it meet all timing requirements?