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Altera_Forum's avatar
Altera_Forum
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15 years ago

IORD IOWR macros vs. memory access to peripherals

What is the point of the IORD and IOWR macros? I can access my custom Avalon peripherals using them, but it seems like I can't access them like the following: volatile alt_u32 *DEV_PTR = DEV_...
Altera_Forum's avatar
Altera_Forum
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15 years ago

Aren't there several ways to avoid issues with the data cache:

1) Don't add a data cache to the nios cpu

2) Get the compiler to use the ldio/stio instructions

3) Use addresses with the top bit set (MMU less systems)

4) If you are using the MMU, don't set the cacheable bit in the TLB

What you do in the C source to get any of these does rather depend

on your system.

There is a compiler flag that is documented to use the ldio/stio instructions for volatile data - but you probably shouldn't use it!