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Altera_Forum's avatar
Altera_Forum
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11 years ago

IORD and IOWR issues

Hello there, I am struggling to understand a simple write and read with the nios processor. With qsys, I have setup a simple testcase where a nios (e) with no cache and a PIO are connected...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I have

- verified the logic on the technology map

- set address bit 31 as you recommended

- on system.h, NIOS2_DCACHE_SIZE and NIOS2_ICACHE_SIZE = 0

still I dont have the expected "10101" in binary from a IOWR of 0xA.

HW: data_out <= {writedata[5:0],1'b1};

Observed behaviour on both the LEDs and with IORD suggest that the implementation is

data_out <= writedata[6:0];

Do you have any other idea how to debug that ?