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Altera_Forum
Honored Contributor
Honored ContributorIORD_16DIRECT causes 2 reads on a 16-bit data bus
A 16-bit write quite rightly performs a single write cycle. A 16-bit read performs two reads, with the next (word) address being read on the second cycle. Why? Simplification of the bus arbit...
Altera_ForumHonored Contributor
Honored ContributorHi, JasonDiplomat
I confuesd the same problem, please see create a new componet(avalon tristate) (http://www.niosforum.com/forum/index.php?act=st&f=2&t=1984) POST 2
