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Altera_Forum
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21 years ago

IORD_16DIRECT causes 2 reads on a 16-bit data bus

A 16-bit write quite rightly performs a single write cycle. A 16-bit read performs two reads, with the next (word) address being read on the second cycle. Why? Simplification of the bus arbit...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Hello,

Searching the forum with the keywords „dynamic AND bus AND sizing” will help to understand the behaviour. Take the Avalon bus specification as a book with golden rules.

Regards,

niosIIuser