IORD_16DIRECT causes 2 reads on a 16-bit data bus

Hi JasonDiplomat,

I hope you don't mind me tagging a question onto your post, but I also have this problem, but with 8-bit access and was about to start a post.

Using Quartus/Nios V5.0, and a Nios II/e CPU, I have created a component as an 8-bit avalon_tristate_slave in Memory slave mode.

When accessing this component, writes take a single bus cycle, but reads, take 4 consecuive cycles, reading from BASE to BASE + 3.

Simple code example:

volatile alt_u8 Test = 0;

*(volatile alt_u8*)BPIO_BIDIR_BASE = Test; // Takes 1 bus cycle (as expected)

Test = *(volatile alt_u8*)BPIO_BIDIR_BASE; // Takes 4 bus cycles (NOT as expected)

This does not seem logical

Can anyone explain what is going on here?