I/O pin states before FPGA configuration

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originally posted by legendbb@Jun 16 2006, 02:52 PM

anyone has idea about what happens on all the pins (fpga unassigned pins, dsp dev kit general i/o pins) before the fpga is confiugred after powing up.

thx

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Answer my own question, for friends who might have the same,

refer to p146 of Stratix II Device Handbook, Apr. 2006