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Honored Contributor
Honored Contributorinterupt disabled in ISR
In the Nios II Software developer's handbook: "the HAL system library disables interupts when it dispatches an ISR". I've examine the file alt_irq_entry.S and alt_irq_handler.c but no pr...
Altera_ForumHonored Contributor
Honored ContributorWhen an exception is generated, the processor performs the following
steps automatically: ■ Copies the contents of the status register (ctl0) to the estatus register (ctl1), saving the pre-exception status of the processor ■ Clears the PIE bit of the status register, disabling further hardware interrupts ■ Stores the address of the instruction after the exception to the ea register (r29), providing the return address for the exception handler to return to ■ Vectors to the exception address
