--- Quote Start ---
Declaring it volatile and making sure that bit 31 is set will ensure that the cache is bypassed. Also, Altera provides HAL functions to remap the address to an uncached address if you don't like doing the bit 31 thing.
Jake
--- Quote End ---
The 'volatile' only ensures that the compiler generate the instruction to write to memory. If the write is cached and the cache isn't write-through (I can't see a definition in the Nios ref book) then the write to memory won't happen until much later.
Additionally you need to leave enough time between the memory write and exiting the ISR for the IRQ to actually have dropped. If you are executing code from tightly coupled memory, the io write requires an Avalon-MM transfer, and you do the write just before returning from the ISR it is possible the ISR will be re-entered.
Honored Contributor
