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Altera_Forum
Honored Contributor
16 years agointerrupt generation
I have an SOPC system with some custom avalon slaves. I would like to generate interrupts to nios with these blocks. I have searched here and on the altera site for documentation on how to implemen...
Altera_Forum
Honored Contributor
16 years ago:confused:
Device drivers typically access control registers associated with their device. These registers are mapped into the Nios II address space. When accessing device registers, the data cache must be bypassed to ensure that accesses are not lost or deferred due to the data cache. For device drivers, the data cache should be bypassed by using the ldio/stio family of instructions. On Nios II cores without a data cache, these instructions behave just like their corresponding ld/st instructions, and therefore are benign. for c programmers, note that declaring a pointer as volatile does notcause accesses using that volatile pointer to bypass the data cache. the
volatile keyword only prevents the compiler from optimizing out
accesses using the pointer.
This volatile behavior is different from the methodology for the first-generation Nios processor.