interrupt generation

The ldio/stio family of instructions explicitly bypass the data cache.

Bit-31 provides an alternate method to bypass the data cache. Using the

bit-31 cache bypass, the normal ld/st family of instructions may be used

to bypass the data cache if the most-significant bit of the address (bit 31)

is set to one. The value of bit 31 is only used internally to the CPU; bit 31

is forced to zero in the actual address accessed. This limits the maximum

byte address space to 31 bits.

Using bit 31 to bypass the data cache is a convenient mechanism for

software because the cacheability of the associated address is contained

within the address. This usage allows the address to be passed to code

that uses the normal ld/st family of instructions, while still

guaranteeing that all accesses to that address consistently bypass the data

cache.

Bit-31 cache bypass is only explicitly provided in the Nios II/f core, and

should not be used for other Nios II cores. The other Nios II cores that do

not support bit-31 cache bypass limit their maximum byte address space

to 31 bits to ease migration of code from one implementation to another.

They effectively ignore the value of bit 31, which allows code written for

a Nios II/f core using bit 31 cache bypass to run correctly on other current

Nios II implementations. In general, this feature is dependent on the

Nios II core implementation.