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Honored Contributor
Honored ContributorInterfacing of Nios-II and Triple Speed Ethernet in Qsys in MII Mode
Hi, In our design we migrate communication to ethernet port. We have Cyclone-IV (E) EP4CE55F484 FPGA with DP83848C Ethernet PHY. We try to interfacing Ethernet PHY with Nios-II. We are using...
Altera_ForumHonored Contributor
Honored Contributortraditionally the TSE is used with two DMAs to read and write packets. The Altera driver used with uCOS and the Nichestack expects two SGDMAs. There is a standard example design on the Altera web site that shows how they are connected here: http://www.altera.com/support/examples/nios2/exm-net-std-de.html
