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Altera_Forum's avatar
Altera_Forum
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16 years ago

Interfacing Custom Component

Recently I built custom component of SDCARD.

What I'm trying to make is an easy interfacing with the SDCARD module I built based on VHDL.

I want to read or write from the SDCARD Mem only by using single write or read command.

When I tried to convert my VHDL module to Custom Component, I have found out that the communication between my module and the AVALON is nothing like the waveforms at the datasheets and at the SOPC software (I'm working with Quartus 9.0).

My problem is when I'm sending threw the NIOS IDE console simple "write" command, the AVALON sending 4 pulses of write on the "write" line instead of one.

And that's not all, at the first pulse I receive threw the "writedata" line, the data I have inserted threw the console, and at the 4th pulse I receive threw the "address" line, the address I asked for (sometimes it's the wrong address).

Another problem I have is when I'm inserting "read" command the AVALON sending me the address on the "writedata" line.

This is very confusing, I don't think its have smth to do with my module, the only thing that I changed from other modules is that the system clk is 50M and the SD clk is 20M.

I added few pictures of the data I receive on the signal tap, and the commands I send threw the console. And here's the index:

PIC1-read mode, the AVALON sends the address to the "writedata" input.

PIC2-while I'm sending threw the NIOS IDE write command, he generate 4 cycles of write, while at the first one he locking the data, and at the last he gives me the address, in this example,he give me the wrong address, i can upload exapmle with the right address at the 4th pulse.

*

Data_in - writedata

Data_out - readadata

*

I can really use some help,

thnx

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  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    --- Quote Start ---

    1 - Your VHDL component. It has a data width of 8 bits correct?. Please read section 3.6.1 of the following document:

    http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

    My recommendation is that you make your component have a 32-bit data width regardless of the fact that you are only going to use 8 bits.

    Jake

    --- Quote End ---

    Sorry if I ask in the same thread, but it's the same thing.

    If I've to write a 16bit FIFO, if I define it as 16 bit wide always avalon master (Nios in my case) shall write it in couple each time it do a write.

    Better explained a Nios Write is 32 bit so from interconnection fabric is "mapped" into 2 16 bit wide write of 16 bit each.

    So if I need to write only 16 bit each time, I can define the fifo as 32 bit wide, then on the read side I connect only the 16 lower bit and then I'll have a 32 bit access on the Nios side will be mapped as 1 only write of all 32 bits of which I loose the 16 high, right?

    But in this case Quartus shall not instanciate the double of the memory right?

    In that case I can trick the avalon bus doing a sort of "avalon wrapper" in order to define the byte enable 4 byte enable all time in which all write are done with the 2 higher byte enable always disabled, whereas I shall define of course the Fifo only 16 bit wide as it is needed in reality.

    Or (sorry if I explain bad, but usually I do not do the software side of the Nios) a IOWR_16DIRECT( address , offset , data ) shall do a single write of only the 16 bit lower of the avalon data bus?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    I have uploaded the tcl file and the VHDL files that attached to the design.

    I will be more that happy if someone will take a look at the component.

    and about "DarkWave" question i don't think i fully understand you'r problem, can you explain?
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Simply:

    On the avalon bus I've attached a NIOS cpu (that is 32 bit) and a 16 bit wide fifo.

    I need that the NIOS can write a defined number of word in the fifo, but the number can change in time and can be 0,1,2,3,4,.. etc..

    Imagine that I'm in the case that the FIFO has to have only 1 message in the fifo.

    The problem is that if the NIOS do a "normal" write on the bus it writes 32 bit so it ends in having 2 msg in my fifo.

    The question is can the NIOS do a IODIREC16_WR on the fifo and so can I have in it only 1 msg in this case?

    Else I've to define the FIFO as 32 bit wide and on the read side consider valid only the lowest 16 bits.

    Thx