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1 - Your VHDL component. It has a data width of 8 bits correct?. Please read section 3.6.1 of the following document:
http://www.altera.com/literature/manual/mnl_avalon_spec.pdf My recommendation is that you make your component have a 32-bit data width regardless of the fact that you are only going to use 8 bits.
Jake
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Sorry if I ask in the same thread, but it's the same thing.
If I've to write a 16bit FIFO, if I define it as 16 bit wide always avalon master (Nios in my case) shall write it in couple each time it do a write.
Better explained a Nios Write is 32 bit so from interconnection fabric is "mapped" into 2 16 bit wide write of 16 bit each.
So if I need to write only 16 bit each time, I can define the fifo as 32 bit wide, then on the read side I connect only the 16 lower bit and then I'll have a 32 bit access on the Nios side will be mapped as 1 only write of all 32 bits of which I loose the 16 high, right?
But in this case Quartus shall not instanciate the double of the memory right?
In that case I can trick the avalon bus doing a sort of "avalon wrapper" in order to define the byte enable 4 byte enable all time in which all write are done with the 2 higher byte enable always disabled, whereas I shall define of course the Fifo only 16 bit wide as it is needed in reality.
Or (sorry if I explain bad, but usually I do not do the software side of the Nios) a IOWR_16DIRECT( address , offset , data ) shall do a single write of only the 16 bit lower of the avalon data bus?
Honored Contributor
