Honored Contributor
Honored ContributorSimply:
On the avalon bus I've attached a NIOS cpu (that is 32 bit) and a 16 bit wide fifo. I need that the NIOS can write a defined number of word in the fifo, but the number can change in time and can be 0,1,2,3,4,.. etc.. Imagine that I'm in the case that the FIFO has to have only 1 message in the fifo. The problem is that if the NIOS do a "normal" write on the bus it writes 32 bit so it ends in having 2 msg in my fifo. The question is can the NIOS do a IODIREC16_WR on the fifo and so can I have in it only 1 msg in this case? Else I've to define the FIFO as 32 bit wide and on the read side consider valid only the lowest 16 bits. Thx
