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Altera_Forum's avatar
Altera_Forum
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17 years ago

Interfacing Custom Component

Recently I built custom component of SDCARD.

What I'm trying to make is an easy interfacing with the SDCARD module I built based on VHDL.

I want to read or write from the SDCARD Mem only by using single write or read command.

When I tried to convert my VHDL module to Custom Component, I have found out that the communication between my module and the AVALON is nothing like the waveforms at the datasheets and at the SOPC software (I'm working with Quartus 9.0).

My problem is when I'm sending threw the NIOS IDE console simple "write" command, the AVALON sending 4 pulses of write on the "write" line instead of one.

And that's not all, at the first pulse I receive threw the "writedata" line, the data I have inserted threw the console, and at the 4th pulse I receive threw the "address" line, the address I asked for (sometimes it's the wrong address).

Another problem I have is when I'm inserting "read" command the AVALON sending me the address on the "writedata" line.

This is very confusing, I don't think its have smth to do with my module, the only thing that I changed from other modules is that the system clk is 50M and the SD clk is 20M.

I added few pictures of the data I receive on the signal tap, and the commands I send threw the console. And here's the index:

PIC1-read mode, the AVALON sends the address to the "writedata" input.

PIC2-while I'm sending threw the NIOS IDE write command, he generate 4 cycles of write, while at the first one he locking the data, and at the last he gives me the address, in this example,he give me the wrong address, i can upload exapmle with the right address at the 4th pulse.

*

Data_in - writedata

Data_out - readadata

*

I can really use some help,

thnx

13 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    This seems to be the behavioral when accessing the slaves with pointers instead of the IORD_DIRECT respectively IOWR_DIRECT function.

    Have a look at the avalon interface specification. if a slave has less data bits than the master, the avalon switch fabric performs the full n bits access from the slave as the master has. therefore i highly recommend to use these IORD_DIRECT functions.

    in your case IOWR_8DIRECT( address , offset , data ) and IORD_8DIRECT( address, data );

    if that does not help, could you please setup signaltap to monitor the avalon interface to your ip (chipselect, address, read, write, waitrequest, data )
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    First thnx for the fast replay

    I have tryed to use DIRECT commands but it had chang nothing.

    The SOPC give me some warning, he advice me to add "byteenable" to my custom although byteenable is affected by the writedata and readdata who have both only 1 byte. (as you can see at the picture)

    So I'm facing 2 choises:

    • I'm adding byteebale with width of 1 bit, the cause is that the consol replay me that the width must be 2,4,6...

    • I'm adding byteebale with width of 2 bit, and the colnsol replay that the byteenable must me one eight of readdata/writedata (8). :confused:
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    yes thats a know bug, i had discussed that with Alteras MySupport.

    If your datawidth is 8 then there is no need for the byteenable as this warning is a bug, so ignore it. but if your datawidth is more than 8 bit (16,32...) then you should add byteenable.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I changed the address width so it will be 2^n in my case 16 lines, and my data width is 8, so the width of the address and data between the NIOS and my custom will be the same. and still, even when I use DIRECT commanditstill doesn't work, do you have any other suggestion for me?

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I think you're heading down the wrong path here. Let's go back to basics.

    1 - Your VHDL component. It has a data width of 8 bits correct?. Please read section 3.6.1 of the following document:

    http://www.altera.com/literature/manual/mnl_avalon_spec.pdf

    My recommendation is that you make your component have a 32-bit data width regardless of the fact that you are only going to use 8 bits.

    2 - Why are you using the PIO macros for acessing your component? I recommend you use the IOWR and IORD macro directly.

    Start with these. If this doesn't fix your problem, let me know.

    Jake
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I fixed the multiply pulses problem, but i still getting the address via the "writedata" signal during read operation. :

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    you mean, during a nios read from your custom ip function the accessed address is displays via writedata and the avalon address lines as well ?

    as long as the avalon write signal is in inactive state, you can ignore the writedata signals.

    writedata is only valid if write is 1
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    that's the problem, I'm recieveing the address only via the "writedata" line.. :confused:

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    then there must be something cluttered

    could you please post your tcl file that describes the connection between the avalon signals and your ip