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20 years ago --- Quote Start --- originally posted by legendbb@Jan 6 2006, 08:51 AM have been building user components for specific hdl design until met on-chip mem bus mapping problem.
i understand one of our nios god (badoman) mentioned, all the legacys are for old designs. but the instantiation option "export bus ports" in "interface to user logic" seems to essential for me and this option is not presented in "user logic"
does any one have detail idea about the difference between using "legacy components --> interface to user logic" & "user logic --> ***(user component)"
i've searched around quartus ii handbook, nios peripheral handbook, sopc datasheet, no useful help.
thanks a lot!
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--- Quote End --- If you use the componet editor to create a new componet, you can export the Avalon Interface signals (address, data etc..) directly if you just add your signals names in the signals tab (and have no HDL files added) - the component editor exports the signals automatically. This should work for slave or master interfaces to your component. I found the following app note to be helpful in understanding directly exported Avalon signals (AN397: Interfacing to external processors) - http://www.altera.com/literature/an/an397.pdf (http://www.altera.com/literature/an/an397.pdf) Although this app note covers exporting a master interface to outside logic it should also apply to a slave interface. Note this only applies to components with no HDL files, if you have HDL files in your component (for interface logic) then you will have to create the additional signals in your top level HDL that "export" the Avalon signals and do the signal mapping inside your HDL code (i.e. assign the Avalon address bus lines to the exported address bus). As I understand it, the component editor should be able to do almost everthing that the old interface to user logic does (although the steps to do it are different). The component editor also has some additional features for building advance components such as a multi-interface component that couldn't be done with the old interface to user logic. I hope this helps. PS. Also you may want to look at "Building memory subsystems using SOPC Builder" in the Quartus II handbook chapter 8 http://www.altera.com/literature/hb/qts/qts_qii54006.pdf (http://www.altera.com/literature/hb/qts/qts_qii54006.pdf) The last sections of this chapter has some useful info on the component editor and off-chip memories.