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Altera_Forum
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21 years ago

Interface to User Logic and DMA...

Hi All, I've got a situation where the IUL and/or DMA components don't fit well. My chip (a USB controller) requires substancially different timing for Read and Write. Additionall...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
21 years ago

Hi Kerri,

I just tightened my joint Read and Write timing as much as I could. It would really be nice though to either (or both) specify separate Read and Write timings or have a wait time (in cpuclocks) in between dma transfers.

Maybe in a future release?

My biggest problem now is getting 8MB/s of data streamed into my Nios system.

Thanks,

Ken